AT VLSI High Level Synthesis Laws: Theory and Practice

As high level synthesis matures in a viable alternative for design of industrial ASIC and rapid scanning of the design solution space, the importance of development of firm and sound theoretical foundations is well recognized. Simultaneously a need for rapid and accurate prediction methodology and tools is becoming widely acknowledged. We attack those two problem by developing AT (area-time) high level synthesis laws. We first establish three AT high level synthesis laws that relate different components of the area of ASIC implementation cost, namely foreground memory, execution units and interconnect, to the sampling period (available time). The laws state that: A = const, AT = const, and AT2 = const for the area of registers, execution units, and interconnect respectively. We validate the correctness of the AT laws using case studies and statistical analysis of synthesis results of 80 real life designs. Several important applications of the AT laws for development of high level synthesis tools are presented. For example, algorithms for area optimization using module selection, power optimization using clock selection, and hierarchical allocation and scheduling are introduced. Use of the AT high level synthesis laws as an effective method for encapsulation of high level synthesis knowledge is also studied. In this framework, the AT laws are used to guide design process and to reason about properties of high level synthesis approaches and algorithms. The effectiveness of the AT laws applications is documented on numerous real life designs.